Many electronic devices employ digital memories, of which there are various types. Static random access memory (SRAM) is one type. In an SRAM, the memory cells employ active devices that are designed to be continuously powered and retain their logic state as long as the static RAM is powered. Another type is referred to as dynamic random access memory (DRAM).
In a DRAM, the signal in each memory cell must be occasionally restored (referred to herein as “refreshed”), so as not to lose the logic state. This is because various factors can cause the stored signal to drift. For example, active devices (e.g., MOSFETs) are typically used to access the memory cells in a DRAM. Leakage currents due to various parasitics associated with these devices, and/or from various other sources, can cause a stored signal to degrade over time. The direction of the change depends on the direction of the leakage currents, which depends in large part on the type of active devices that are used to access the memory cells. If N-channel MOSFETs are used to access the memory cells, then the direction of the leakage current is usually to VSS. If P-channel MOSFETs are used, then the direction of the leakage current is to VDD. Unchecked, these effects would, over time, cause drifts so large that the logic state of the signal is lost, i.e., the signal changes from a level that represents a first logic state to a level that represents a second logic state.
FIG. 1 shows an example of the drift and the refresh that occurs in a DRAM that uses N-channel MOSFETs to access the memory cells. A signal for a memory cell at a high logic state and a signal for a memory cell at a low logic state are shown. In this DRAM memory cells at a high logic state are refreshed to 0.8 VDD. The memory cells at a low logic state are refreshed to 0.2 VDD. In can be seen that both signals decrease over time. The decrease does not create a problem in regard to the signal representing a low logic state, because the decrease causes the voltage to get closer to zero, i.e., closer to the ideal voltage for a low logic state. The decrease however can create a problem for the signal intended to represent a high logic state. This is because over time and without a refresh, the voltage would eventually reach the low voltage state. Because the low logic state becomes “stronger” over time (i.e., the voltage gets closer to the ideal voltage for the low logic state) it is referred to herein as the “stronger” logic state. Because the high logic state becomes “weaker” over time (i.e., the voltage gets further from the ideal voltage for the high logic state) it is thus referred to as the “weaker logic state”.
Refresh is usually carried out by an operation referred to as a read and write-back operation. Note that a pair of data lines (often referred to as bit lines, or BL and NOT BL) are typically used to read from and/or write to a memory cell. One of the bit lines is used to connect to the memory cell through an access device. The other bit line is used as a reference signal.
FIG. 2 shows the signal timing commonly used for a read and write-back operation. The operation has three phases: (1) a pre-charge phase (typically carried out while the address is being decoded), (2) a charge sharing phase in which the memory cell is connected to, and shares charge with, one of the bit lines, and (3) a latch phase in which the logic state of the memory cell is sensed (i.e., detected), latched, and written back into the memory cell. The three phases are further discussed below.
First note however, that the bit line BL is shown starting the pre-charge phase with a voltage near VDD, and the bit line NOT BL is shown starting the pre-charge phase with a voltage near zero volts. This assumes that the previous read and write-back operation resulted in a high logic state on BL and a low logic state on NOT BL. It should be recognized that this will not always be the case. In some instances, the previous read and write-back operation results in a low logic state on BL and a high logic state on NOT BL. In such instances, BL starts the pre-charge phase with a voltage near zero volts, and NOT BL starts the pre-charge phase with a voltage near VDD. Note that the memory cell is shown starting with a voltage that is approximately 0.7VDD, which corresponds to a high logic state.
In the pre-charge phase, each of the bit lines is pre-charged to a midrail voltage, i.e., ½ VDD. This prepares the bit lines for reading the data from the memory cell. Pre-charging to ½ VDD eliminates the need for reference cells, which had been commonly used in earlier, NMOS DRAMS. Note that the voltage of the memory cell does not change during the pre-charge phase.
In the charge sharing phase, BL is connected to a memory cell. This causes the bit line BL to share charge with the memory cell, which causes the voltage on BL to change (shown as a small increase). The change is usually relatively small (e.g. 100 millivolts, because the capacitance of the bit line is usually much greater than the capacitance of the memory cell). The direction of the change depends on the logic state of the memory cell. The change is positive if the memory cell has a high logic state (as shown in FIG. 2). The change is negative if the memory cell has a low logic state (for example, a voltage in the range from 0.2 VDD to zero volts).
Once the charge sharing phase is complete, the logic state of the memory cell can be determined by comparing the voltage on the bit line BL to the voltage on the bit line NOT BL. If the voltage of the bit line BL is greater than the voltage of the bit line NOT BL, then the memory cell is at a high logic state. If the voltage of the bit line BL is less than the voltage of the bit line NOT BL, then the memory cell is at a low logic state.
In this instance the voltage on the bit line BL is greater than the voltage on the bit fine NOT BL, signifying that the memory cell had been at a high logic state. If the memory cell had been at a low logic state, then voltage of the memory cell would have been less than the voltage of the reference cell, and the decrease on BL would have been greater than the decrease on NOT BL.
The latch phase is used to sense and latch the logic state of the memory cell (based on the voltages on the bit lines BL, NOT BL) and to restore the signal in the memory cell. In the latch phase, BL remains operatively connected to the memory cell. The bit line with the higher of the two voltages, which in this instance is BL, is driven high (e.g., toward VDD). The bit line with the lesser of the two voltages, which in this instance is NOT BL, is driven low (e.g., toward zero). At the end of the latch phase, the voltage on BL indicates the logic state of the memory cell. The signal in the memory cell is restored as the bit line BL is driven high (or low).
DRAMs have traditionally been provided in the form of dedicated integrated circuits (ICs). Such ICs are typically incorporated into an electronic device, along with one or more other ICs, such as for example, an IC for a digital information processor, an IC for an analog to digital converter, etc.
However, in order to reduce the size, speed, cost and/or power requirements of electronic devices, efforts have been made to bring DRAM memories (particularly high density digital DRAM memories) and other function(s) together onto a single IC. Digital memories that have been embedded onto an IC along with other function(s) are commonly referred to as “embedded” memories. There is now a desire to improve embedded DRAMs, for example to reduce the size, increase the density, increase the access speed, reduce the cost, increase the yield and reliability, and/or reduce the power requirements (for example in active mode and/or in standby mode).
Designers face various challenges with respect to achieving these objectives. Some of these challenges have to do with the need to refresh the memory cells. For example, memory cells must be refreshed even if the system and DRAM are in standby mode (e.g., where the DRAM is powered so as to retain the data, but is not accessible). Because the memory cells must be refreshed, the refresh circuitry continues to operate and draw power, even in standby mode. The impact on standby power may be significant, especially in the case where the electronic device has limited energy from which to draw on. This is particularly the case for small, battery powered electronic devices, e.g., hand held mobile phones. One reason for the high refresh power in standby mode is that many refresh circuits employ a charge pump. These charge pumps are customarily sized to handle the relatively high loads encountered in the active mode (i.e., normal operating mode), and therefore require as much power in standby mode as in the active mode.
In addition, memory cells are usually not accessible (to a processor) while the memory cells are being refreshed. This inaccessibility can stall a processor needing to access data in the memory cells. Note that the electrical time constant of the memory cells limits how quickly the signals can be refreshed. Also note that the electrical time constant often increases as DRAMs are made smaller and more dense. A stall rate that is as little as one percent can have a significant impact on system performance.
There are other challenges as well. For example, in order to reduce memory cycle time, it is common to shorten the duration of the write-back (latch) phase. However, this usually means that the latch phase does not last long enough for the voltage in the memory cell to reach VDD. Recall that the electrical time limits how quickly the signal in the memory cell can be restored. For example, the latch phase may be made just long enough for the voltages on the bit lines to reach 0.8 VDD (rather than VDD) for a high logic state and 0.2 VDD (rather than zero) for a low logic low state. The voltage often gets as low as 0.6 VDD prior to refresh.
The above technique of reducing the duration of the write-back phase can create difficulties for designers and manufacturers seeking to provide embedded DRAMs that are smaller, faster, more reliable, and/or require less power. First, cell voltages between 0.8 VDD and 0.6 VDD provide less drive than voltages between VDD and 0.8 VDD. Less drive makes it more difficult to tolerate higher cell time constants, therefore making it more difficult to reduce the size of the DRAM. In addition, less drive also makes it more difficult to reduce cell access time (i.e., increase the speed of the DRAM) and more difficult to increase bit line loading (another common technique to reduce the size of the DRAM). Moreover, because the cells have lower voltages, the cells have less immunity to soft errors and switching noise, and less tolerance for leakage current, thereby making it more difficult to increase yield.
Thus, notwithstanding the level of performance provided by current embedded DRAMs, there remains a desire for further enhancements, for example, to provide embedded DRAMs that are smaller (higher density), faster, more reliable, and/or require less power (in active mode and/or in standby mode).